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| Both sides previous revision Previous revision Next revision | Previous revision | ||
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en:example_of_development_around_the_ad9959_dds [2016/03/14 08:42] fwiotte |
en:example_of_development_around_the_ad9959_dds [2016/03/14 08:44] (current) fwiotte |
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| FR1 default value = 0x00; | FR1 default value = 0x00; | ||
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| - | This registry allows others to define the internal PLL and the multiplier x4 to x20. For example, the value to be provided to enable EN1 = x20 ⇒ 0xD00000 PLL; In this case it is sufficient to provide a quartz 25MHz PLL with activated PIN x20 clock was 500MHz 22 and 23 of the DDS. | + | This registry allows others to define the internal PLL and the multiplier x4 to x20. For example, the value to be provided to enable EN1 = x20 ⇒ 0xD00000 PLL; In this case it is sufficient to provide a quartz 25MHz PLL with activated PIN x20 clock was 500MHz 22 and 23 of the DDS. |
| The third register is the register table CFR 29 datasheet | The third register is the register table CFR 29 datasheet | ||
| Line 55: | Line 55: | ||
| CFR default value = 0x302; | CFR default value = 0x302; | ||
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| - | This register defines the different register DDS.Ce operating mode is important if you use | + | This register defines the different register DDS.Ce operating mode is important if you use certain |
| - | certain modes of operation: frequency sweep, phase or amplitude. Important default output are DAC full-scale current mode. | + | modes of operation: frequency sweep, phase or amplitude. Important default output are |
| + | DAC full-scale current mode. | ||
| The fourth register is the register CFTW0: Table 29 datasheet | The fourth register is the register CFTW0: Table 29 datasheet | ||
en/example_of_development_around_the_ad9959_dds.1457941324.txt.gz · Last modified: 2016/03/14 08:42 by fwiotte
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