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en:example_of_development_around_the_ad9959_dds

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en:example_of_development_around_the_ad9959_dds [2016/03/14 08:38]
fwiotte
en:example_of_development_around_the_ad9959_dds [2016/03/14 08:43]
fwiotte
Line 45: Line 45:
     FR1 serial address = 0x01;     FR1 serial address = 0x01;
     FR1 default value = 0x00;     FR1 default value = 0x00;
 +    ​
 +    This registry allows others to define the internal PLL and the multiplier x4 to x20. For example, the value to be provided to enable EN1 = x20 ⇒ 0xD00000 PLL; In this case it is sufficient to provide a quartz 25MHz PLL with activated PIN x20 clock was 500MHz 22 and 23 of the DDS.
 +
 +The third register is the register table CFR 29 datasheet
 +
 +    register CFR (Channel Function Register)
 +    three bytes is assigned to When this register: number of register bytes
 +    CFR serial address = 0x03;
 +    CFR default value = 0x302;
 +    ​
 +This register defines the different register DDS.Ce operating mode is important if you use certain
 +modes of operation: frequency sweep, phase or amplitude. Important default output are
 +DAC full-scale current mode.
 +
 +The fourth register is the register CFTW0: Table 29 datasheet
 +
 +    CFTW0 register (Channel Frequency Tuning Word 01)
 +    oven bytes is assigned to When this register: number of register bytes
 +    CFTW0 serial address = 0x04;
 +    CFTW0 default value = 0x00;
 +    ​
 +This register to return the desired frequency according to the relation below:
 +
 +    FTW0 = output frequency x 2 ^ 32 / frequency clock
 +        ​
 +The registry is the fifth CPOW0 table 29 of the datasheet register
 +
 +    CPOW0 register (Channel Phase Offset Word 01)
 +    two bytes is assigned to When this register: number of register bytes
 +    CPOW0 serial address = 0x05;
 +    CPOW0 default value = 0x00;
 +    ​
 +This register defines the phase of the output signal coded on 14 bits with the following relationship:​
 +
 +    CPOW0 Delta phi = x ^ 2 14/360 °
 +         
 +The sixth register is the ACR register: Table 29 datasheet
 +
 +    ACR register (Amplitude Control Register)
 +    two bytes is assigned to When this register: number of register bytes
 +    CAB serial address = 0x06;
 +    ACR default value = 0x00;
 +    ​
 +This register sets the amplitude. By default amplitude is programmable full scale mode, but if you change the CFR register.
 +
 +The other registers are useful to program the DDS for scans frequencies,​ phases and amplitudes in others.
 +
 +    FR2 register (Function Register 2)
 +    LSRR register (Linear Sweep Ramp Rate1)
 +    FDW register (LSR Falling delta word1)
 +    RDW register (LSR Risingdelta word1)
 +    CW1 register (Channel Word 1)
 +    ...
en/example_of_development_around_the_ad9959_dds.txt · Last modified: 2016/03/14 08:44 by fwiotte